1. Field of the Invention
The present invention relates to an oscillator circuit and the present invention particularly relates to an electronic oscillator circuit, the oscillator amplitude of which is controllable.
2. Description of the Related Art
In LC oscillators, it is often necessary to guarantee a certain output amplitude apart from the frequency. A safe control of circuits downstream of the LC oscillator is to be ensured by such a output amplitude. Such a circuit downstream of an LC oscillator can, for example, be a frequency divider circuit (=divider), as is, for example, illustrated in FIG. 6. The frequency divider circuit 600 includes an input IN for applying a signal having the frequency f0. The input IN of the divider circuit 600 preferably includes a first input terminal 602 and a second input terminal 604 between which a difference signal can be applied. Furthermore, the divider circuit 600 includes a first operating transistor T1, a second operating transistor T2, a third operating transistor T3 and a fourth operating transistor T4. In addition, the divider circuit 600 includes a first current source 606 and a second current source 608. Additionally, the divider circuit 600 includes eight further transistors which in the following description will be referred to as a fifth transistor T5 to a twelfth transistor T12. The transistors here can, for example, be designed as self-locking n-channel enhancement MOSFETs. As an alternative, npn bipolar transistors may also be employed. When MOS transistors are chosen as the operating transistors T1 to T4, they will have an equal relation of channel width W to channel length L. Additionally, the divider circuit 600 includes a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4. Furthermore, the divider circuit 600 comprises an output OUT having a first output terminal 610 and a second output terminal 612 and a supply voltage terminal 614 and a ground connection 616. An alternating voltage can be tapped between the first output terminal 610 and the second output terminal 612, wherein a frequency f0 of the alternating voltage which can be tapped at the output OUT corresponds to half the frequency f0 of a signal at the input IN.
Each of the transistors T1 to T12 illustrated in FIG. 6 comprises a control input 620 and a first terminal 622 and a second terminal 624. For reasons of clarity, the control input 620, the first terminal 622 and the second terminal 624 are indicated in FIG. 6 only for the first operating transistor T1. In analogy, the identification of the control terminal 620 and of the first terminal 622 and the second terminal 624, however, also applies to the other transistors T2 to T12 illustrated in FIG. 6, wherein the first terminals 622 of the respective transistors are always formed by the upper terminals illustrated in FIG. 6 and the second terminals 624 of the respective transistors are always formed by the lower terminals. With regard to connecting the above-mentioned elements of the divider circuit 600, the first input terminal 602 of the circuit input IN is conductively connected to the control terminal of the second operating transistor T2 and to the control terminal of the third operating transistor T3. The second input terminal 604 of the circuit input IN is conductively connected to the control terminal 620 of the first operating transistor T1 and to the control terminal of the fourth operating transistor T4. Furthermore, the second terminal 624 of the first operating transistor T1 is conductively connected to the second terminal of the second operating transistor T2. Additionally, the second terminal 624 of the first operating transistor T1 is connected to the ground terminal 616 via the first current source 606 and the second terminal of the third operating transistor T3 is conductively connected to the second terminal of the fourth operating transistor T4. In addition, the second terminal of the third operating transistor T3 is connected to the ground terminal 616 via the second current source 608. Additionally, the second terminal of the fifth transistor T5 and the second terminal of the sixth transistor T6 are conductively connected to the first terminal 620 of the first operating transistor T1. In analogy, the second terminal of the seventh transistor T7 and the second terminal of the eighth transistor T8 are conductively connected to the first terminal of the second operating transistor T2. Also in analogy, the second terminal of the ninth transistor T9 and the second terminal of the tenth transistor T10 are conductively connected to the first terminal of the third operating transistor T3. Furthermore, the second terminal of the eleventh transistor T11 and the second terminal of the twelfth transistor T12 are conductively connected to the first terminal of the fourth operating transistor T4. The first terminal of the fifth transistor T5 is conductively connected to the control terminal of the seventh transistor T7, to the first terminal of the eighth transistor T8, to the control terminal of the tenth transistor T10 and, via the resistor R1, to the supply terminal 614. Furthermore, the first terminal of the sixth transistor T6 is conductively connected to the first terminal of the seventh transistor T7, to the control terminal of the eighth transistor T8, to the control terminal of the ninth transistor T9 and, via the resistor R2, to the supply voltage terminal 614. In addition, the first terminal of the ninth transistor T9 is conductively connected to the first output terminal 610, to the control input of the eleventh transistor T11, to the first terminal of the twelfth transistor T12, to the control terminal of the fifth transistor T5 and, via the resistor R3, to the supply terminal 614. In addition, the first terminal of the tenth transistor T10 is conductively connected to the first terminal of the eleventh transistor T11, to the control terminal of the twelfth transistor T12, to the control terminal of the sixth transistor T6, to the second output terminal 612 and, via the resistor R4, to the supply terminal 614.
In order to bring the divider circuit 600 into operation, a supply voltage is to be applied between the supply terminal 614 and the ground terminal 616, the supply voltage defining a maximal voltage at the output OUT of the divider circuit 600, i.e., between the first output terminal 610 and the second output terminal 612, via the resistors R3 and R4. The operating transistors T1 to T4 can be controlled by a voltage signal to be applied at the input IN, i.e., between the first input terminal 602 and the second input terminal 604, such that a signal at the input IN of the divider circuit 600, having a frequency f0 can be transformed in a manner that a nearly rectangular signal having half the frequency f0 applied at the input IN is output at the output OUT of the divider circuit 600. The level of the rectangular signal basically varies between the potential of the supply voltage terminal 614 and a low voltage level decoupled from the ground potential by the second current source 608. A current I0 flows through the first current source 606 and the second current source 608. It is also to be pointed out here that all the voltages are decoupled with regard to a potential of the ground terminal 616 via corresponding current sources. The potential of the transistors T5 to T12 is thus determined by the potential of the supply terminal 614, while the potential of the operating transistors T1 to T4 is determined by the VCO potential and the voltage between the input terminals 602 and 604.
In order to be able to perform an intended frequency division, a first bistable circuit group of the transistors T1, T2, T5, T6, T7 and T8 and a second bistable circuit group of the transistors T3, T4, T9, T10, T11 and T12 are connected to each other such that the first bistable circuit group controls the second bistable circuit group and vice versa. For such a frequency-division behavior of the divider circuit 600, however, there is a precondition that the operating transistors T1 to T4 and the transistors T5 to T12 nearly have the effect of an ideal switch. This can only be ensured when a voltage amplitude Û at the input IN is sufficiently large so that the operating transistors T1 to T4 either connect through nearly without any loss or block nearly ideally. If the voltage amplitude Û between the first input terminal 602 and the second input terminal 604 is not sufficiently large, the operating transistors T1 to T4 will not connect through ideally, the result being a signal at the output OUT of the divider circuit 600, which is affected by partially high level variations partly outside a tolerance region between the ideal levels of zero volt and the supply voltage. If such an output signal with high level variations is then used for another circuit downstream of the divider circuit 600, a perfect function of the downstream circuit cannot be ensured.
Such a behavior of an oscillator circuit is particularly problematic when there is a high temperature dependence of the voltage amplitude Û of the oscillator at the input IN, i.e. of an amplitude between the first input terminal 602 and the second input terminal 604. With such a high temperature dependence, an error-free functioning of an oscillator circuit having an oscillator and the divider circuit 600 illustrated in FIG. 6 can no longer be ensured. This particularly means that the quality of the frequency-divided signal at the output OUT of the divider circuit 600 is strongly dependent on temperature.
Such a temperature dependence of the oscillator amplitude is illustrated in FIG. 7A. In order to ensure that an oscillator circuit is as temperature-independent as possible, a high but constant current can, for example, be fed to the voltage-controlled oscillator in order to obtain such a high oscillator amplitude Û still having, after a frequency division by the divider circuit 600, the required quality. Such a required quality of the oscillator amplitude Û can, for example, be for the level of the oscillator amplitude Û only to vary within a tolerance region around the two ideal levels mentioned above. A current Icontrol which must be fed in is, for example, illustrated in FIG. 7B. Such a procedure, however, is of the disadvantage that with some temperature ranges, in particular with low temperature ranges where the signal amplitude Û provided by the oscillator is large enough anyway for a sufficiently precise switching behavior of the divider circuit 600, even without an additional feed current, too large a current is fed to the oscillator, the result being an unnecessary increase in losses.